This invention relates to circuits employing field effect transistors, and in particular to a technique for substantially increasing the speed of operation of circuits employing complementary field effect transistors.
2. Description of the Prior Art
In MOS circuits the speed of operation is limited by resistance and capacitance, the resistance of an MOS transistor driving the capacitance of the next MOS transistor. Because the output current of an MOS transistor is proportional to its channel width, if a narrow transistor is employed to drive a high capacitance load, a very long delay would result. To reduce this delay in digital circuits, a series of cascaded inverters are frequently used. In such circuits the time delay for each stage is proportional to the fan-out of that stage, which is the ratio of the size (channel width) of the driven device or devices to that of the driving device or devices. Thus, the choice of relative sizes of the driving and driven devices affects the speed of the circuit.
Because the speed of any given inverter stage is a constant times the fan-out of that stage, if a specified fan-out is to be driven using a series of inverters, there are many possible choices. For example, consider a total fan-out of 100. If a single inverter with a fan-out of 100 is employed (a 4-micron width stage driving a 400-micron width stage), then the circuit will have a delay of 100 units of time because the delay is a constant times the fan-out. Alternatively, if we are not concerned with the polarity of the output, two serial inverter stages could be employed, each with a fan-out of 10. This provides a total fan-out for the circuit of 10 times 10 or 100, yet this driving arrangement has a delay of only 20 units of time (two delays, each of ten units of time). If four inverters are employed, each will have a fan-out of the square root of 10 and the total circuit delay will be four times the square root of 10, or about 12.65 units of time.
Thus, a circuit designer is presented with a range of choices for the number of stages to drive a given size load. There is an optimum number of stages; however, at which the total delay for the circuit is minimized, and that total delay may not be further reduced using conventional techniques. This minimum delay is reached when the size of each stage is e (the base of natural logarithm-approximately 2.7) times the size of the previous stage. In other words, for maximum speed the total channel width of the devices in any stage is approximately 2.7 times the total channel width of the devices in the preceding stage.
A basic complementary field effect transistor inverter includes a PMOS device connected between a positive supply and an output node and an NMOS device connected between the output node and a negative supply with the gates connected in parallel and to the input. For example, see the inverter between nodes 7 and 8 in FIG. 1. In such an inverter the input signal going high (to the positive supply voltage) turns off the PMOS device to disconnect the common output node from the high potential, and turns on the NMOS device to pull the output node low by connecting it to the negative supply potential, usually zero volts or ground. Because an NMOS device is approximately twice as conductive as a PMOS device for a given gate width and turn-on voltage, by making the NMOS device approximately half the width of the PMOS device, the inverter will have approximately the same delay for both high-to-low or low-to-high logic transitions.
A short channel transistor has both low on resistance and low capacitance which minimizes switching time. The channel length of all transistors is therefore the minimum allowed by the manufacturing technology employed.
In all following discussions, transistor sizes refer to transistor channel width with the understanding that all channel lengths are the minimum allowed by the technology. In a typical inverter chain, a first inverter might include a 10-micron PMOS device and a 5-micron NMOS device. The following inverter (with near optimum fan-out of approximately three) therefore would include a 30-micron PMOS device and 15-micron NMOS device. The third inverter would have a 90-micron PMOS device and a 45-micron NMOS device, etc. In the first inverter the 5-micron NMOS device is driving both a 30-micron PMOS device and 15-micron NMOS device in the second inverter for total of 45 microns, or an NMOS fan-out of 9. Similarly, the 10-micron PMOS device in the first inverter is driving a 30-micron PMOS device and a 15-micron NMOS device in the second inverter for a PMOS fan-out of 4.5. Because the PMOS device is half as conductive as an NMOS device of the same size, the 10-micron PMOS will have a delay equivalent to that of the 5-micron NMOS driving the same load.
In each stage the NMOS device turns on the PMOS device and turns off the NMOS device in the following inverter. Likewise, in each stage, the PMOS device turns on the NMOS device and turns off the PMOS device in the following inverter. Because in each inverter the PMOS device is twice the size of the NMOS device, two-thirds of the charge from the previous NMOS device will go to the PMOS device and one-third will go to the NMOS device. Similarly, the PMOS device in each inverter will send one-third of its charge to the NMOS device in the following inverter and two-thirds to the PMOS device in the following inverter. Thus, charge from each device in a preceding stage is supplied to two devices in a following stage.
One form of CMOS logic in which speed is somewhat enhanced with respect to the inverter chain technique described above is domino logic. See, e.g., R.H. Krambeck, et al., "High-Speed Compact Circuits with CMOS," IEEE Journal of Solid-State Circuits (June, 1982) SC-17(3):614-619.
In domino logic circuits, an array of transistors is configured to perform a specified logic function. The output node is precharged to a particular voltage level (typically high for NMOS) while all current paths to the other voltage level (ground for NMOS) are turned off. During this phase the input to each of the gates of all transistors in the circuit are set to the desired level. Next, the current path to the high level is turned off by a clock signal, and the path to ground is turned on. Depending on the states of the input signals, the output node will either float at the high level or be pulled down, thereby evaluating the logic function implemented by the transistor array. The transition from precharge to evaluation is accomplished by a single clock edge applied simultaneously to all gate electrodes in the circuit. FIG. 5 of the above paper shows a typical domino logic circuit.
Domino logic, however, suffers from several disadvantages relative to the present invention. It operates at undesirably low speed because each logic gate drives an inverter consisting of both a PMOS and an NMOS transistor. It has low throughput because the multiple sequential stages receive a common precharge clock signal, and thus one complete clock cycle is required for each logic operation. Additionally, domino logic does not provide logic functions in both NMOS and PMOS. Furthermore, in both the inverter chains and domino logic prior art, the logic functions are performed by changes in voltage levels. Because changes in the levels of output nodes are sensed after the circuit reaches a steady state condition, new input information cannot be applied until the final output of the domino chain in question is stable. This results in delays until the entire circuit stabilizes, even though only a small portion may be changing.
Other prior art is listed in an accompanying disclosure statement.